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automotive power data sheet rev. 1.1, 2012-10-19 tle8080em engine management ic for small engines tle8080em TLE8080-2EM
data sheet 2 rev. 1.1, 2012-10-19 tle8080em table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 5v supply, reset and supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 5v supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 power on reset and reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 watchdog operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 electrical characteristics 5v supply, re set and supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 low side switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 electrical characteristics lo w side switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 variable reluctance sensor (vrs) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1 electrical characteristics vr sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.2 spi protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.2.1 spi register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.2.2 set and reset of diagnosis register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.3 electrical characteristics spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9k-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1 k-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2 electrical characteristics k-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table of contents
pg-ssop24 type package marking tle8080em pg-ssop24 tle8080em TLE8080-2EM pg-ssop24 TLE8080-2EM data sheet 3 rev. 1.1, 2012-10-19 engine management ic fo r small engines tle8080em 1overview features ? supply 5v (+/-2%), 250ma ? k-line transceiver (iso 9141) ? serial peripheral interface (spi) ? 4 low side driver for inductive loads with overtemperature and overcurrent protection and open load/short to gnd in off diagnosis: ? 2 low side switches with maximum operation of 2.6a ? 2 low side switches with maximum operation of 350ma ? 1 low side driver for resistive loads with maximum operation current of 3a including overtemperat ure and overcurrent protection ? configurable variable reluctance sensor interface ? reset output and 5v undervoltage detection ? watchdog ? green product (rohs compliant) ? aec qualified description the tle8080em is an engine management ic based on in fineon smart power technology (spt). it is protected by embedded protection functions and integrates a power s upply, k-line, spi, variable reluctance sensor interface and power stages to drive different loads in an engi ne management system. it provides a compact and cost optimized solution for engine management systems. it is very suitable for one cylinder motorcycle engine management systems. TLE8080-2EM this version differs from the main version in the parameters ? v5dd reset threshold for TLE8080-2EM ? and ? power on reset delay time ? in chapter 5.4 . for ordering conditions please contact the nearest infineon technologies office.
data sheet 4 rev. 1.1, 2012-10-19 tle8080em block diagram 2 block diagram figure 1 block diagram 5v voltage supply k-line ls driver inductive loads 350ma ls driver resistive loads 3a spi 4 vr sensor 2 2 vs rx; tx csn; si; so; sclk v5dd kio out4 out3 out2 out1 vr_in1; vr_in2 vr_out reset nro agnd pgnd in3 in1 ls driver inductive loads 2.6a watchdog undervoltage detection ls driver inductive loads 2.6a wd_dis out5 ls driver inductive loads 350 ma
tle8080em pin configuration data sheet 5 rev. 1.1, 2012-10-19 3 pin configuration 3.1 pin assignment figure 2 pin configuration 3.2 pin definitions and functions pin symbol function 1kio k-line bus connection 2vs battery voltage: block to agnd directly at the ic with min. 100nf ceramic capacitor 3out5 output channel 5 4out4 output channel 4 5out3 output channel 3 6pgnd power ground: internally connected to pin 9, connect externally to pin 9 7out2 output channel 2 8out1 output channel 1 9pgnd power ground: internally connected to pin 6, connect externally to pin 6 10 vr_in1 vr sensor interface input 1 11 vr_in2 vr sensor interface input 2 12 wd_dis watchdog disable: high active; internal pull down 13 vr_out vr sensor output 14 so spi slave output: high impedance 15 si spi slave input: internal pull down 16 sclk spi clock input: internal pull down 17 csn spi chip select input: low active; internal pull up pg-ssop-24 .vsd tx rx kio csn sclk si so v5dd nro wd_dis vr_out out4 out3 vr_in1 vr_in2 in3 in1 out1 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 agnd vs 14 13 11 12 pgnd out2 pgnd out5 25 pgnd
data sheet 6 rev. 1.1, 2012-10-19 tle8080em pin configuration 18 in1 control input channel 1: internal pull down 19 in3 control input channel 3: internal pull down 20 nro reset output: low active, open drain 21 v5dd 5v supply output: connected to external blocking capacitor 22 agnd analog ground: connected to system logic ground 23 rx k-line receive output: logic output of data received from the k-line bus kio 24 tx k-line transmit input: logic level input for data to be transmitted on the k-line bus kio; internal pull up 25 exposed pad substrate connection: must be connected to pgnd externally on pcb pin symbol function
tle8080em general product characteristics data sheet 7 rev. 1.1, 2012-10-19 4 general product characteristics table 1 absolute maximum ratings 1) t j = -40c to +150c: all voltages with respect to ground unless otherwise specified. positive current flowing into pin (unless otherwise specified) 1) not subject to production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. voltages supply voltage vs v vs -0.3 ? 40 v ? 4.1.1 supply voltage v5dd v v5dd -0.3 ? 5.5 v ? 4.1.2 input voltage on pins in1, in3, sclk, si, wd_dis v x -0.3 ? 5.5 v ? 4.1.3 input voltage on pins csn, tx v x -0.3 ? v5dd +0.3v v ? 4.1.3 input voltage vr_in1, vr_in2 v vr_in1/2 -0.3 ? 5.5 v see also 4.2.1 and 4.2.2 4.1.4 dc voltage on pins out1-5, kio v x -0.3 ? 30 v respect to pgnd all channels and kio are switched off 4.1.5 dc voltage on pins vr_out, so, rx, nro v x -0.3 ? 5.5 v i x <1ma 4.1.6 dc voltage agnd to pgnd v x -0.3 ? 0.3 v 4.1.7 dc voltage on pin kio v kio -0.3 ? 35 v respect to pgnd kio is switched off 4.1.8 currents input current between vr_in1 and vr_in2 i vr_in1,vr_in2 -? ? 50 ma ? 4.2.1 input current vr_in1, vr_in2 to gnd i vr_in1/2,gnd -? ? 10 ma ? 4.2.2 temperatures junction temperature t j -40 ? 150 c ? 4.3.1 storage temperature t stg -55 ? 150 c ? 4.3.2 esd susceptibility esd resistivity all pins to gnd v esd -2 ? 2 kv hbm 2) 2) esd susceptibility, hbm acco rding to eia/jesd 22-a114b 4.4.1 esd resistivity all pins to gnd v esd -500 ? 500 v cdm 3) 3) esd susceptibility, charged device model ?cdm? eia/jesd22-c101 or esda stm5.3.1 4.4.2 esd resistivity pin 1, 12, 13, 24 (corner pins) to gnd v esd1,19,20,36 -750 ? 750 v cdm 3) 4.4.3
data sheet 8 rev. 1.1, 2012-10-19 tle8080em general product characteristics notes 1. stresses above the ones listed here may cause perma nent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection func tions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. pr otection functi ons are not designed for continuous repetitive operation. note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. table 2 functional range parameter symbol values unit note / test condition number min. typ. max. supply voltage v s 6 ? 18 v ? 4.5.1 junction temperature t j -40 ? 150 c ? 4.5.2 table 3 thermal resistance parameter symbol values unit note / test condition number min. typ. max. junction to case r thjc ?7?k/w 1) 1) not subject to production test, specified by design 4.6.1 junction to ambient r thja ?29?k/w 1) 2) 2) specified r thja value is according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm boar d with 2 inner copper layers (2 x 70m cu, 2 x 35m cu). where applicable a thermal via array under the ex posed pad contacted the first inner copper layer. 4.6.2
tle8080em 5v supply, reset and supervision data sheet 9 rev. 1.1, 2012-10-19 5 5v supply, reset and supervision 5.1 5v supply the tle8080em integrates a voltage regulator for load currents up to 250ma. the input voltage at vs is regulated to 5v on v5dd with a precision of 2%. the design allows to achieve stable operation even with ceramic output capacitors down to 470 nf. it is protected against overlo ad, short circuit, and over temperature conditions. for low drop operation, a charge pump is implemented. figure 3 5v supply 5.2 power on reset and reset output the reset output nro is an open drain output. when the level of v v5dd reaches the reset threshold ( v rt ) (increasing voltage v v5dd ) the signal at nro remains low for the power-up reset delay time ( t rd ). the reset function and timing is illustrated in figure 4 . the reset reaction time ( t rr ) avoids wrong triggering caused by short ?glitches? on the v5dd-line. in case of v5dd power down (decreasing voltage; v v5dd < v rt for t > t rr ) a logic low signal is generated at the pin nro to reset an external micro controller. the level of the reset threshold for increasing v v5dd is for the hysteresis ( v rh ) higher than the level for decreasing v v5dd . with an active reset all power stages and the k-line output are disabled and spi commands are ignored. + - vref v5dd vs e.g. c i v5dd i vs
data sheet 10 rev. 1.1, 2012-10-19 tle8080em 5v supply, reset and supervision figure 4 reset timing diagram 5.3 watchdog operation the tle8088ee integrates a watchdog function which monitors the correct spi communication with the micro controller. a watchdog disable pin ( wd_dis ) with an inte rnal pull down current source is implemented. with a high level the watchdog function is disabled. for enabled watchdog function a fter power-up reset delay time ( t rd ), valid spi communica tion from the micro controller must occur within the watchdog period ( t wp ) specified in the electrical ch aracteristics. a restart of the watchdog period is done with a low to high transition of the csn pin of a valid transmission of a 16 bit message. a reset is generated (nro goes low) for the time ( t wr ) if there is no restart during the watchdog period as shown in figure 5 . status after watchdog overflow: ? all outputs are switched off ? spi registers are not influenced ? watchdog time out bit in spi status register is set ? first answer to spi communication is the content of the status register switching o f outputs and reset of watchdog time out bit after watchdog overflow: ? outputs 1 and 3 will be switched on with an positive edge at in1 respectively in3 ? outputs 2, 4 and 5 will be switched on with a write command to cmd register ? the watchdog time out bit will be reset with the rising edge of csn of the first read command of the status register v s t v v5dd t v rt < t rr v nro t v nro _h t rd t rr t rr v nro _l t rd
tle8080em 5v supply, reset and supervision data sheet 11 rev. 1.1, 2012-10-19 figure 5 watchdog timing diagram t vs v 5dd v nro watchdog period csn t rd v rt 1. correct spi communication no correct spi communication within the watchdog period causing reset t t t t t rr t wr normal operation t wp si t 16 bits 16 bits e.g. 4 bits 16 bits restart
data sheet 12 rev. 1.1, 2012-10-19 tle8080em 5v supply, reset and supervision 5.4 electrical characteristics 5v supply, reset and supervision table 4 electrical characteristics: 5v supply, reset and supervision v s =13.5v, t j = -40c to +150c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. 5v supply output voltage v v5dd 4.9 5 5.1 v 0 ma < i v5dd < 250ma 6v < v s < 18v 5.1.1 output current limitation i v5dd 250? 650ma v v5dd = 0v 5.1.2 load regulation v v5dd, lo ? ? 50 mv 1 ma < i v5dd < 250ma 5.1.3 line regulation v v5dd, li ??10mv i v5dd = 1ma 10v < v s < 18v 5.1.4 power supply rejection psrr ?60?db f = 100hz v s, ripple = 0.5 vpp 1) 5.1.5 output capacitor c v5dd 470 ? ? nf 1) 5.1.6 output capacitor esr esr(c v5dd ) ??10 1) 5.1.7 current consumption i vs ?5.58ma i v5dd = 0ma, all channels and k- line off 5.1.8 low drop voltage v v5dd 4.8 ? 5 v i v5dd = 1ma v s =5v 5.1.9 4.15 ? 5 v i v5dd = 250ma v s =5v; after device ramp-up ( v s >9v) 5.1.10 over temperature protection over temperature threshold t ot 150? 200c 1) 5.2.1 over temperature hysteresis t ot,hys ?20?c 1) 5.2.2 under voltage detection v5dd reset threshold v rt 4.00 4.25 4.50 v v v5dd decreasing only at version tle8080em 5.3.1 reset hysteresis v rh 10 ? 150 mv 5.3.2 v5dd reset threshold for TLE8080-2EM v rt 3.4 3.65 3.9 v v v5dd decreasing only at version TLE8080-2EM 5.3.3
tle8080em 5v supply, reset and supervision data sheet 13 rev. 1.1, 2012-10-19 power on reset power on reset delay time t rd 10 15 20 ms only at version tle8080em 5.4.1 30 40 50 ms only at version TLE8080-2EM 5.4.2 reset reaction time t rr 10 15 20 s 5.4.3 reset output nro low level output voltage v nro,l ??1.1v i nro = 1ma 5.5.1 watchdog watchdog period t wp 50 60 70 ms 5.6.1 watchdog reset time t wr 120 240 360 s5.6.2 input characteristics wd_dis low level input voltage v wd_dis,l ??1v 5.7.1 high level input voltage v wd_dis,h 2??v 5.7.2 pull down current i wd_dis,pd 20 50 100 aat v in = 5v 5.7.3 pull down current i wd_dis,pd 2.4 ? ? aat v in = 0.6v 5.7.4 hysteresis v wd_dis,hys 30 250 mv 5.7.5 1) not subject to production test, specified by design table 4 electrical characteristics: 5v supply, reset and supervision (cont?d) v s =13.5v, t j = -40c to +150c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
data sheet 14 rev. 1.1, 2012-10-19 tle8080em power stages 6 power stages 6.1 low side switches the power stages are built by n-channel power mosfet transistors. the channels are universal multi channel switches, but are mostly suitable to be used in engine management systems. within an engine management system, the best fit of the channels to the typical loads is: ? channel 1 and 3 for injector valves or similar sized solenoids with a maximum operation current requirement of 2.6a ? channel 2 for malfunction indication lamps or other re sistive loads with a maximum current requirement of 3a ? channel 4 and 5 for relays or other inductive loads with a maximum current requirement of 350ma the channels are switch ed off while reset is active (pin nro is lo w). after an power on reset the channels will be switched on with a positive edge at in1 respectively in3 or with a switch on command over spi. figure 6 low side switches in table 5 the control concept, typical loads, the implem ented protection and monito r functions are illustrated. table 5 overview diagnosis function channel control recommended load over temperature over current open load/short to gnd 1 pin in1 injector valve x latch 1) 1)reset behavior of the diagnosis bits see chapter 8.2 x 2 spi cmd register bit 0 mil (max. 3w) x repetitive switching; off time t oc,off 1) ? 3 pin in3 valve x latch 1) x 4 spi cmd register bit 1 relay one temperature sensor for channel 4 and channel 5 latch 1) x 5 spi cmd register bit 2 relay one temperature sensor for channel 4 and channel 5 latch 1) x v bat i d v dscl out v ds gnd l , r l i d out v ds gnd r channel 1, 3, 4, 5 channel 2 v bat
tle8080em power stages data sheet 15 rev. 1.1, 2012-10-19 in overcurrent cond ition the affected channel will be switched off. there are tw o different implementations for switching on again after an over current event. for channels 1, 3, 4 and 5 the switch of f state is latched. the input pins in1, in3 must be set to low to reset the latch before the channel can be switched on again. for channels 4 and 5 the over current status is reset with a write command to the cmd register. the switching state is according to the status of bit 1 and 2. channel 2 will be swit ched off and after t oc_off = 5ms typically the channel will be switched on again automatically. the result is repetitive switching with a fixed off time of t oc,off . the overcurrent status of channel 2 is internally latched. for releasing the over current diagnosis bit after over current condit ion, channel 2 must stay switched on for at least t oc,st . the bits 0 to 4 in the stat register reflect the actual switching status of the channels. for detailed description see chapter 8.2.2 . all the channels are prot ected from over temper ature. in an overtemp erature situation the affected channel will be switched off. the channel will restart operation if the junction temperat ure decreases by thermal shutdown hysteresis t ot,hys . channels 4 and 5 are using a common temperat ure sensor. therefore, the two channels are switched together during over temperature. for channels 1, 3, 4 and 5 an open load/short to gnd in off detection with a pull do wn current source (active in off) and a comparator is implemented. in case of switch off and the output voltage is below the open load detection threshold (v outx < v ol,th ), the open load in off timer is started. after the open load in off delay time t ol,d , the open load is detected (timing see figure 9 and figure 10 ). the diagnosis status of the ch annels is monitored in the spi diagnosis register diag (see chapter 8.2 ).
data sheet 16 rev. 1.1, 2012-10-19 tle8080em power stages 6.2 electrical characteris tics low side switches table 6 electrical characteristics: power stage v s =13.5v, t j = -40c to +150c: all voltages with respect to ground. positive current flowing into pin (unless otherwise specified). parameter symbol values unit note / test condition number min. typ. max. output channel 1 and 3 on resistance r outx_on ?0.60.7 i outx_nom = 1.3a; t j = 150c 6.1.1 output clamp ing voltage v outx_cl 30 35 40 v i outx = 0.02a 6.1.2 over-current switch off threshold i outx_oc 2.6 ? 5 a 6.1.3 over-current switch off filter time t oc,f 0.5 ? 3 s6.1.4 over temperature switch off t ot 150? 200c 6.1.5 over temperature hysteresis t ot,hys ? 20 ? c 6.1.6 open load in off detection threshold v ol,th 2 2.8 3.2 v 6.1.7 open load in off pull down diagnosis current i ol 50 100 150 a v outx = 13.5v 6.1.8 open load in off diagnosis delay time t ol,d 100 ? 200 s6.1.9 turn on delay time t d,on ?0.251 s v outx = 13.5v i outx = 1.3a, resistive load 1) 6.1.10 turn off delay time t d,off ?0.91.5 s v outx = 13.5v i outx = 1.3a, resistive load 1) 6.1.11 turn on time t s,on ?0.61.2 s v outx = 13.5v i outx = 1.3a, resistive load 1) 6.1.12 turn off time t s,off ?0.61.2 s v outx = 13.5v i outx = 1.3a, resistive load 1) 6.1.13 output leakage current in off mode i outx_off ??3 a v outx = 13.5v t j = 150c 2) 6.1.14 output channel 2 on resistance r outx_on ?1.11.2 i outx_nom = 0.3a; t j = 150c 6.2.1 over-current switch off threshold i outx_oc 3 ? 6.5 a 6.2.2 over-current switch off filter time t oc,f 0.5 ? 3 s6.2.3 over-current switch off time t oc,off 3?8ms 6.2.4
tle8080em power stages data sheet 17 rev. 1.1, 2012-10-19 over-current status time t oc,st 1 ? 12 ms 6.2.5 over temperature switch off t ot 150? 200c 6.2.6 over temperature hysteresis t ot,hys ? 20 ? c 6.2.7 turn on delay time t d,on ?0.61.2 s v outx = 13.5v i outx = 1.3a, resistive load 1) 6.2.8 turn off delay time t d,off ?0.71.5 s v outx = 13.5v i outx = 1.3a, resistive load 1) 6.2.9 turn on time t s,on ?0.41 s v outx = 13.5v i outx = 1.3a, resistive load 1) 6.2.10 turn off time t s,off ?0.41 s v outx = 13.5v i outx = 1.3a, resistive load 1) 6.2.11 output leakage current in off mode i outx_off ??3 a v outx = 13.5v t j = 150c 6.2.12 output channel 4 and 5 on resistance r outx_on ?3.33.6 i outx_nom = 0.3a; t j = 150c 6.3.1 output clamp ing voltage v outx_cl 30 35 40 v i outx = 0.02a 6.3.2 over-current switch off threshold i outx_oc 350? 600ma 6.3.3 over-current switch off filter time t oc,f 0.8 ? 2.4 s6.3.4 over temperature switch off t ot 150? 200c 6.3.5 over temperature hysteresis t ot,hys ? 20 ? c 6.3.6 open load in off detection threshold v ol,th 2 2.8 3.2 v 6.3.7 open load in off pull down diagnosis current i ol 50 100 150 a v outx = 13.5v 6.3.8 open load in off diagnosis delay time t ol,d 100 ? 200 s6.3.9 turn on delay time t d,on ?0.51.2 s v outx = 13.5v i outx = 0.3a, resistive load 1) 6.3.10 turn off delay time t d,off ?0.71.5 s v outx = 13.5v i outx = 0.3a, resistive load 1) 6.3.11 table 6 electrical characteristics: power stage (cont?d) v s =13.5v, t j = -40c to +150c: all voltages with respect to ground. positive current flowing into pin (unless otherwise specified). parameter symbol values unit note / test condition number min. typ. max.
data sheet 18 rev. 1.1, 2012-10-19 tle8080em power stages figure 7 timing low side switches channel 1 and 3 turn on time t s,on ?0.10.8 s v outx = 13.5v i outx = 0.3a, resistive load 1) 6.3.12 turn off time t s,off ?0.10.8 s v outx = 13.5v i outx = 0.3a, resistive load 1) 6.3.13 output leakage current in off mode i outx_off ??2 a v outx = 13.5v t j = 150c 2) 6.3.14 input characteristic in1 and in3 low level input voltage v in,l ??1v 6.4.1 high level input voltage v in,h 2??v 6.4.2 input voltage hysteresis v in,hys 50 110 250 mv 6.4.3 pull down current i in,pd 20 50 100 a v in = 5v 6.4.4 pull down current i in,pd 2.4 ? ? a v in = 0.6v 6.4.5 1)definition of timing see figure 7 or figure 8 2) in off mode open load diagnosis pull down current active table 6 electrical characteristics: power stage (cont?d) v s =13.5v, t j = -40c to +150c: all voltages with respect to ground. positive current flowing into pin (unless otherwise specified). parameter symbol values unit note / test condition number min. typ. max. t t v in x v outx v batt 80 % 20 % t d,on t s, o n t d,off t s, o f f 50 %
tle8080em power stages data sheet 19 rev. 1.1, 2012-10-19 figure 8 timing low side switches channel 2,4 and 5 figure 9 timing open load/short to gnd in off detection channel 1 and 3 t t v batt 80 % 20 % t d,on t s, o n t d,off t s, o f f v csn 50 % v outx t t v inx v outx v batt v ol.th t ol .d 50% t chx_ol t ol. d open open
data sheet 20 rev. 1.1, 2012-10-19 tle8080em power stages figure 10 timing open load/short to gnd in off detection channel 2,4 and 5 t v outx v batt v ol.th t ol .d t v csn 50% t chx_ol t ol. d open open
tle8080em variable reluctance se nsor ( vrs ) interface data sheet 21 rev. 1.1, 2012-10-19 7 variable reluctance se nsor ( vrs ) interface the variable reluctance (vr) sensor interface converts an output signal of a vr sensor into a logic level signal suited for c 5v input ports. the voltage difference between the two input pins, vr_in1 and vr_in2 , which are connected to the two output pins of the vr sensor, is detected and the output pin vr_out is switched depending on the sign of the voltage difference ( see figure 12 )the amplitude of the vr sensor signal is limited by an internal clamping circuit to avoid damage of the device due to over voltage caused by the vr sensor signal. figure 11 vr sensor interface block diagram clamp & load detection vr_out 2,5v buffer select load select threshold vr_in1 vr_in2
data sheet 22 rev. 1.1, 2012-10-19 tle8080em variable reluctance se nsor ( vrs ) interface 7.1 electrical characteris tics vr sensor interface table 7 electrical characteristics: vr sensor interface v s =13.5v, t j = -40c to +150c: all voltages with respect to ground. positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. input characteristics: positive vr sensor interface detection threshold v vr,th_pos -30 0 30 mv 7.1.1 negative vr sensor interface detection threshold v vr,th_neg -80 -50 -20 mv cmd register: vr_t[1:0] = ?00? reset state 7.1.2 -130 -100 -70 mv cmd register: vr_t[1:0] = ?01? 7.1.3 -550 -500 -450 mv cmd register: vr_t[1:0] = ?10? 7.1.4 -1.1 -1 -0.9 v cmd register: vr_t[1:0] = ?11? 7.1.5 vr sensor interface load selection r vr,load 30 75 120 k t j = 25c; cmd register: vr_l[1:0] = ?00? reset state 7.1.6 90 k t j = -40c; cmd register: vr_l[1:0] = ?00? reset state 60 k t j = 150c; cmd register: vr_l[1:0] = ?00? reset state 34.58k cmd register: vr_l[1:0] = ?01? 7.1.7 1.5 2.2 3.3 k cmd register: vr_l[1:0] = ?10? 7.1.8 0.7 1.2 1.9 k cmd register: vr_l[1:0] = ?11? 7.1.9 vr sensor interface input clamping current i vr,clamp ??50ma 7.1.10 vr sensor interface input clamping voltage v vr,clamp 2.5 3 3.5 v i vr,clamp = 50ma 7.1.11 output characteristics: low level output voltage v vr_out,l ??0.3v i vr_out = 100 a7.2.1 high level output voltage v vr_out,h v5dd- 0.3 ??v i vr_out = -100 a7.2.2
tle8080em variable reluctance se nsor ( vrs ) interface data sheet 23 rev. 1.1, 2012-10-19 figure 12 timing characteristics of the vr sensor interface transfer characteristics: delay time input to vr_out falling edge t dr 11.52.5 s7.3.1 delay time input to vr_out rising edge t df 11.52.5 s7.3.2 table 7 electrical characteristics: vr sensor interface (cont?d) v s =13.5v, t j = -40c to +150c: all voltages with respect to ground. positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. v vr _ out t t t dr t df v vr_in1 ? vr_in2 v vr t h_pos =0v 50% v vr t h_neg
data sheet 24 rev. 1.1, 2012-10-19 tle8080em serial peripheral interface (spi) 8 serial peripheral interface (spi) the diagnosis and control interface is based on a serial peripheral interface (spi). the spi is a 16 bit full duplex synchronous se rial slave interface, which uses four lines: si , so , sclk and csn . 8.1 spi signal description csn - chip select: the system micro controller sele cts the ic by means of the csn pin. whenever the pin is in low state, data transfer can take place. as long as csn is in high state, all signals at the sclk and si pins are ignored and so is forced to high impedance. csn - high to low transition: so changes from high impedance to high or lo w state depending on the status flag (see chapter 8.2 ). csn - low to high transition: end of transmission, the validation check of the communi cation is done (number of bits and valid command) and valid commands are executed. sclk - serial clock: this input pin clocks the internal shift register. the serial input (si) transfers data into the shift register on the falling edge of sclk while the serial output (so) shifts information out on the rising edge of the serial clock. it is essential that the sclk pin is in low state whe never chip select csn makes any transition. si - serial input: serial input data bits are shifted in at this pin, the most significant bit (msb) first. si information is re ad on the falling edge of sclk. please refer to section 8.2 for further information. so - serial output: data is shifted out serially at this pin, the msb first. so is in high impedance until the csn pin goes to low. the output level before the first rising edge of sclk depends on the status flag. new data will appear at the so pin following the rising edge of sclk. please refer to section 8.2 for further information. 8.2 spi protocol the principle of the spi communication is shown in figure 13 . the message from the micro controller must be sent msb first. the data from the so pin is sent msb first. the tle8080em samples data from the si pin on the falling edge of sclk and shifts data out of the so pin on the rising edge of sclk. each access must be terminated by a rising edge of csn. all spi messages must be exactly 16-bits long , otherwise the spi message is discarded. there is a one message delay in t he response to each message (i.e. th e response for message n will be returned during message n+1). the spi protocol of the tle8080em provides three regist ers. the control register, the diagnosis, and the status register. the control register contains the set up bits for the vr sensor interface and the control bits of channels 2, 4 and 5. the diagnosis register cont ains the diagnosis bits of the five low side switches. the status register contains the status bits of the five low side switches, the watchdog status bit, and the watchdog time out bit. after power-on reset, all register bits are set to reset state (see chapter 8.2.1 ).
tle8080em serial peripheral interface (spi) data sheet 25 rev. 1.1, 2012-10-19 there are four ways of valid access: ? write access to the command register: the answer is 1 for the r/w bit, 00 for the address and the content of the register ? read access to the command register: the answer is 0 for the r/w bit, 00 for the address and the content of the register ? read access to the diagnosis register: the answer is 0 for the r/w bit, 01 for the address and the content of the register ? read access to the status register: the answer is 0 for the r/w bit, 10 for the address and the content of the register any other access is recognized as an invalid message. status flag indication: after the falling edge of csn and before the first rising edge of sclk , the level of the so indicates the status of the diagnosis register: ? so = ?0?: no error condition detected; all diagnosis register bits are ?0? ? so = ?1?: one or more error conditions are detect ed; one or more diagnosis register bits are ?1? with this feature during every spi co mmunication a check of the diagnosis status can be done without additional read access of the diagnosis register. figure 13 spi protocol spi answers: ? during power on reset: spi commands are ignored, so is always low ? after power on reset: the content of the command register is transmitted with the next spi transmission ? during watchdog reset: spi commands are ignored, so has the value of the status flag ? after watchdog overflow: the content of the status register is tr ansmitted with the first spi transmission after the low to high transition of nro ? after a read or write command: the content of the selected register is transmitted with the next spi transmission ? after an invalid communication: the content of the diag nosis register is transmitted with the next spi transmission bit 15 msb bit 0 lsb don?t care don?t care clock 1 clock 2 clock 3 clock 15 clock 16 bit 14 bit 13 bit 1 don?t care bit 0 lsb bit 15 msb bit 14 tristate tristate time time time time don?t care bit 1 bit 13 sclk si so csn status flag * ) * ) active clock edge for reading data at si
data sheet 26 rev. 1.1, 2012-10-19 tle8080em serial peripheral interface (spi) 8.2.1 spi register overview 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r /w ad1 ad0 field bits type description ad1:ad0] [14:13] w address bits: 00 b control register 01 b diagnosis register 10 b status register r /w 15 w read - write bit: 0 b read access 1 b write access cmd register command register (identifier x00x xxxx xxxx xxxx b )reset value: 0 h 1514131211109 876543210 r /w ad1 ad0 vr_t1 vr_t0 vr_l1 vr_l0 ctr5 ctr4 ctr2 rw rw rw rw rw rw rw field bits type description ctr2 0rw control bit channel 2: 0 b channel 2 is switched off (reset state) 1 b channel 2 is switched on ctr4 1rw control bit channel 4: 0 b channel 4 is switched off (reset state) 1 b channel 4 is switched on ctr5 2rw control bit channel 5: 0 b channel 5 is switched off (reset state) 1 b channel 5 is switched on vr_l1: vr_l0 [10:9] rw load register of vr interface: ( c.f. vr sensor interface load selection ) 00 b r load = 75 k (reset state) 01 b r load = 4.5 k 10 b r load = 2.2 k 11 b r load = 1.2 k
tle8080em serial peripheral interface (spi) data sheet 27 rev. 1.1, 2012-10-19 vr_t1: vr_t0 [12:11] rw threshold register of vr interface: 00 b -50 mv (reset state) 01 b ? 100 mv 10 b ? 500 mv 11 b ? 1 v diag register diagnosis register (identifier x01x xxxx xxxx xxxx b )reset value: 0 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r /w ad1 ad0 ch45_ ot ch5_ oc ch5_ ol ch4_ oc ch4_ ol ch3_ ot ch3_ oc ch3_ ol ch2_ ot ch2_ oc ch1_ ot ch1_ oc ch1_ ol rrrrrrrrrrrrr field bits type description ch1_ol 0r open load diagnosis bit of channel 1: 0 b no open load in off detected (reset state) 1 b open load in off detected ch1_oc 1r over current diagnosis bit of channel 1: 0 b no over current detected (reset state) 1 b over current detected ch1_ot 2r over temperature diagnosis bit of channel 1: 0 b no over temperature detected (reset state) 1 b over temperature detected ch2_oc 3r over current diagnosis bit of channel 2: 0 b no over current detected (reset state) 1 b over current detected ch2_ot 4r over temperature diagnosis bit of channel 2: 0 b no over temperature detected (reset state) 1 b over temperature detected ch3_ol 5r open load diagnosis bit of channel 3: 0 b no open load in off detected (reset state) 1 b open load in off detected ch3_oc 6r over current diagnosis bit of channel 3: 0 b no over current detected (reset state) 1 b over current detected ch3_ot 7r over temperature diagnosis bit of channel 3: 0 b no over temperature detected (reset state) 1 b over temperature detected ch4_ol 8r open load diagnosis bit of channel 4: 0 b no open load in off detected (reset state) 1 b open load in off detected ch4_oc 9r over current diagnosis bit of channel 4: 0 b no over current detected (reset state) 1 b over current detected field bits type description
data sheet 28 rev. 1.1, 2012-10-19 tle8080em serial peripheral interface (spi) 8.2.2 set and reset of diagnosis register bits set of the over current diagnosis bits of channels 1, 3, 4 and 5: the over current diagnosis bits of channels 1, 3, 4 an d 5 are set asynchronously of the internal clock with the output signal of the detection circuit (details see chapter 6.1 ). ch5_ol 10 r open load diagnosis bit of channel 5: 0 b no open load in off detected (reset state) 1 b open load in off detected ch5_oc 11 r over current diagnosis bit of channel 5: 0 b no over current detected (reset state) 1 b over current detected ch45_ot 12 r over temperature diagnosis bit of channel 4 and 5: 0 b no over temperature detected (reset state) 1 b over temperature detected stat register status register (identifier x10x xxxx xxxx xxxx b )reset value: 0 h 15141312 11109876543210 r /w ad1 ad0 wd_dis wd_to st5 st4 st3 st2 st1 r r rrrrr field bits type description st1 0r status bit channel 1: 0 b channel 1 is switched off (reset state) 1 b channel 1 is switched on st2 1r status bit channel 2: 0 b channel 2 is switched off (reset state) 1 b channel 2 is switched on st3 2r status bit channel 3: 0 b channel 3 is switched off (reset state) 1 b channel 3 is switched on st4 3r status bit channel 4: 0 b channel 4 is switched off (reset state) 1 b channel 4 is switched on st5 4r status bit channel 5: 0 b channel 5 is switched off (reset state) 1 b channel 5 is switched on wd_to 11 r watchdog time out bit: 0 b no watchdog time out 1 b watchdog time out occurred wd_dis 12 r watchdog status bit: 0 b watchdog enabled (v wd_dis = 0v) 1 b watchdog disabled (v wd_dis = 5v) field bits type description
tle8080em serial peripheral interface (spi) data sheet 29 rev. 1.1, 2012-10-19 reset of the over current diagnosis bits of channels 1 and 3: ? diagnosis register was read out: ? input pin inx remains high: no reset of the over current diagnosis bit, the channel remains switched off ? input pin inx transition from high to low: the over current diagnosis bit is reset, the channel could be switched on again ? diagnosis register was not read out ? channel remains switched off and no reset of the over current diagnosis bit is done ? input pin inx is low: with the next read access of the diagno sis register the diagnosis bits are reset reset of the over current diagnosis bits of channels 4 and 5: ? diagnosis register was not read out ? channel remains switched off and no reset of the over current diagnosis bit is done ? diagnosis register was read out: ? spi command register write command is not sent: no reset of the over current diagnosis bit, the channel remains switched off ? spi command register write command is sent: the over current diagnosis bit is reset, the channel will be switched according the status of the control bit set and reset of the over current diagnosis bit of channel 2: the over current diagnosis register bi t for channel 2 is set asynchronously of the internal clock with the output signal of the detection circuit. with this signal the output is switched o ff and the counter for the off time t oc,off of the repetitive switching cycle starts. after t oc,off the channel will be switched on again . with an remaining over current condition the channel will be s witched on repetitively. this internal overcurrent status of the channel is latched internally. the internal over current status is reset in two situations. ? over current condition exists no longer: the internal over current stat us is reset after the time t oc,st ? over current condition remains and the channel is switched off: the internal over curren t status is reset after the time t oc,off the reset of the over current diagnosis register bit for ch annel 2 is related to the internal over current status. in figure 14 and figure 15 the behavior of the diagnosis with tempor ary and permanent over current condition is drawn.
data sheet 30 rev. 1.1, 2012-10-19 tle8080em serial peripheral interface (spi) figure 14 behavior of diagnosis with temporary over current condition at channel 2 figure 15 behavior if diagnosis with permane nt over current condition at channel 2 reset of the over temperature diagnosis bits: i out2 cont reg. bit 1 internal over current status diag reg. bit 3 i d,oc over current no over current spi diag reg. read out spi diag reg. read out spi diag reg. read out t oc,off t oc,off t oc,st t oc,f t oc,f t oc,f i out2 cont reg. bit 1 internal over current status diag reg. bit 3 i d,oc permanent over current spi diag reg. read out spi diag reg. read out spi diag reg. read out t oc,off t oc,off t oc,off t oc,f t oc,f t oc,f
tle8080em serial peripheral interface (spi) data sheet 31 rev. 1.1, 2012-10-19 the over temperature diagn osis bits will be reset with read access of the diagnosis regi ster if no over temperature condition is detected. reset of the open load in off diagnosis bits: the open load in off diagnosis bits will be reset with read access of the diagnos is register if no open load condition is detected.
data sheet 32 rev. 1.1, 2012-10-19 tle8080em serial peripheral interface (spi) 8.3 electrical characteristics spi table 8 electrical characteristics: spi v s =13.5v, t j = -40c to +150c: all voltages with respect to ground. positive current flowing into pin (unless otherwise specified). parameter symbol values unit note / test condition number min. typ. max. input characteristics (csn, sclk, si): low level input voltage v x,l ??1v 8.1.1 high level input voltage v x,h 2??v 8.1.2 hysteresis v x,hys 50 250 mv pull up current csn i x,pu -25 -50 -100 aat v in = 0v 8.1.3 pull up current csn i x.pu -25 ? ? aat v in = v v5dd - 0.6v 8.1.4 pull down current sclk, si i x,pu 20 50 100 aat v in = v v5dd 8.1.5 pull down current sclk, si i x.pu 2.4 ? ? aat v in = 0.6v 8.1.6 output characteristics (so): low level output voltage v so,l ??0.4v i x = 100 a 8.2.1 high level output voltage v so,h v5dd- 0.4 ??v i x = -100 a 8.2.2 output high impedance leakage current i so,tri -3 ? 3 a0v < v so < 5v 8.2.3 timings: lead time t 1 210 ? ? ns csn falling to sclk rising 8.3.1 lag time t 2 75 ? ? ns sclk falling to csn rising 8.3.2 csn high time t 3 550 ? ? ns csn rising to csn falling 8.3.3 period of sclk t 4 200 ? ? ns 8.3.4 sclk to csn set up time t 5 10 ? ? ns sclk falling to csn falling 8.3.5 sclk low time t 7 60 ? ? ns 8.3.6 csn to sclk hold time t 8 15 ? ? ns csn rising to sclk rising 8.3.7 si set up time t 9 30 ? ? ns si set up time to sclk falling 8.3.8 si hold up time t 10 30 ? ? ns si holdup time after sclk falling 8.3.9 so enable time t 11 ? ? 165 ns csn falling to so active 8.3.10 so valid time t 12 ? ? 120 ns so data valid after sclk rising 8.3.11
tle8080em serial peripheral interface (spi) data sheet 33 rev. 1.1, 2012-10-19 figure 16 spi timing diagram so disable time t 13 ? ? 165 ns so high impedance after csn rising 8.3.12 number of clock pulses while csn = low 16 ? 16 pulses 8.3.13 so rise time t so_rise ? ? 75 ns 20% to 80%, c load =1.6pf 8.3.14 so fall time t so_fall ? ? 75 ns 80% to 20% c load =1.6pf 8.3.15 table 8 electrical characteristics: spi (cont?d) v s =13.5v, t j = -40c to +150c: all voltages with respect to ground. positive current flowing into pin (unless otherwise specified). parameter symbol values unit note / test condition number min. typ. max. bit 15 msb bit 0 lsb don?t care don?t care clock 1 clock 2 clock 3 clock 15 clock 16 bit 14 bit 13 bit 1 don?t care bit 0 lsb bit 15 msb bit 14 tristate tristate time time time time don?t care bit 1 bit 13 sclk si so t 6 t 4 t 7 t 1 t 5 t 10 t 9 t 11 t 12 t 2 t 3 t 8 t 13 csn status flag
tle8080em k-line data sheet 33 rev. 1.1, 2012-10-19 9k-line 9.1 k-line the k-line module is a serial link bus interface de vice designed to provide bi-directional half-duplex communication interfacing. it is designed to interface vehicles via the special iso k-line and meets the iso standard 9141. the device?s k-line bus driver?s output is protected against bus shorts. figure 17 k-line block diagram vs v5dd rx tx kio driver & protection
data sheet 34 rev. 1.1, 2012-10-19 tle8080em k-line 9.2 electrical char acteristics k-line table 9 electrical characteristics: k-line v s =13.5v, t j = -40c to +150c: all voltages with respect to ground. positive current flowing into pin (unless otherwise specified). parameter symbol values unit note / test condition number min. typ. max. output rx low level output voltage v rx,l ??0,4v i rx = 100 a9.1.1 high level output voltage v rx,h v5dd- 0.4 ??v i rx = -100 a9.1.2 input tx low level input voltage v tx,l ??1v 9.2.1 high level input voltage v tx,h 3.2 ? ? v 9.2.2 hysteresis v tx,hys 280 500 700 mv 9.2.3 pull up current i pu_l -70 -100 -150 aat v tx = 0v 9.2.4 pull up current i pu_l -30 ? ? aat v tx = v v5dd - 0.6v 9.2.5 k-line bus driver input/output kio low level output voltage v kio,o,l ? ? 1.4 v tx = low, r kio =480 9.3.1 current limitation i kio(lim) 40 ? 140 ma 9.3.2 low level input voltage v kio,i,l ? ? 0.4* vs v9.3.3 high level input voltage v kio,i,h 0.6* vs ??v 9.3.4 hysteresis v kio,i,hys 0.02 * vs ? 0.175 * vs v9.3.5 pull down current i kio,pd 51015 a 9.3.6 transfer characteristics c rx = 25pf; r kio = 540 ; c kio 1.3nf receive frequency f kio,rec ??500khzc kio = 0pf 9.4.1 transmit frequency f kio,tran ? ? 100 khz 9.4.2 delay time kio -> rx rising edge 1) 1) for definition see figure 18 t drr 0.05 ? 0.5 sc rx,load = 1.6pf 9.4.3 delay time kio -> rx falling edge 1) t dfr 0.05 ? 0.5 sc rx,load = 1.6pf 9.4.4 delay time tx -> kio rising edge 1)2) 2) not subject of production test, behavior defined by external devices t drt 0.05 ? 0.5 sc kio,load = 1.6pf 9.4.5 delay time tx -> kio falling edge 1) t dft 0.05 ? 0.5 sc kio,load = 1.6pf 9.4.6
tle8080em k-line data sheet 35 rev. 1.1, 2012-10-19 figure 18 k-line transfer characteristics v txd t v v5dd v bus t v rxd t t drr t dfr t drt t dft v s 0.7*v s 0.3*v s 0.5*v v5dd 0.5*v v5dd v v5dd
data sheet 36 rev. 1.1, 2012-10-19 tle8080em package outlines 10 package outlines figure 19 pg-ssop24 green product (rohs compliant) to meet the world-wide customer requirements for enviro nmentally friendly products, and to be compliant with government regulations, the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). pg-ssop-24-4-po v01 1) does not include plastic or metal protrusion of 0.15 max. per side 112 24 13 2) does not include dambar protrusion of 0.13 max. 8.65 ?.1 c 0.1 a-b 2x 0.65 0.25 2) m c 0.2 d 24x ?.05 a-b b a index marking c (1.47) 1.7 max. 0.08 c seating plane ?.1 3.9 1) 0.35 x 45? ?.25 0.64 ?.2 d 6 m 0.2 d +0 -0.1 0.1 stand off +0.06 0.19 8? max. cd 2x 0.1 bottom view 24 1 6.4 ?.25 2.65 13 12 ?.25 for further info rmation on alternative pa ckages, please visit our website: http://www.infineon.com/packages . dimensions in mm
tle8080em revision history data sheet 37 rev. 1.1, 2012-10-19 11 revision history revision date changes 1.0 2012-09-12 data sheet 1.1 2012-12-19 parameter 5.4.3, page 13 reset reaction time increased
edition 2012-10-19 published by infineon technologies ag 81726 munich, germany ? 2012 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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